1. Field of the Invention
The present invention relates to a high-resolution data converter, particularly to a calibration method towards a high-resolution data converter.
2. Description of the Related Art
A U.S. Pat. No. 7,893,853 disclosed a “DAC variation-tracking calibration” technology, which uses a set of LSB (Least-Significant Bit) dummy cells to calculate the sum of the LSBs as a standard value and compares the standard value with each MSB (Most-Significant Bit), and which calibrates the value of each MSB to approximate the standard value by adjusting the output of the sub-DAC in each MSB. However, the prior art has a disadvantage of a large area overhead because it costs an additional sub-DAC for each MSB.
Y. Cong and R. Geiger published in IEEE J. Solid-State Circuit vol. 38, pp. 2051-2059, December 2003 a paper “A 1.5-V 14-b 100 MS/s Self-Calibrated DAC,” wherein a high-resolution 16-bit ADC is used to calibrate a 14-bit DAC. During booting, the prior art uses a high-resolution ADC to estimate the errors of the MSB current sources of the DAC one by one in a foreground calibration mode. Then, the estimated errors of the MSB current sources are used to compute the calibrated outputs. The prior art has two disadvantages:    1. The resolution of the ADC must be at least 2-bit higher than that of the DAC, resulting in a requirement of a pretty high-resolution ADC. Therefore, the prior art needs a very complicated circuit.    2. The area of the required high-resolution ADC is much larger than that of the DAC itself
Yusuke Ikeda, Matthias Frey, and Akira Matsuzawa published in IEEE Asian Solid-State Circuit Conference Nov. 12-14, 2007 a paper “A 14-bit 100 MS/s Digitally Calibrated Binary-Weighted Current-Steering CMOS DAC without Calibration ADC,” wherein a 8-bit sub-DAC and 3 calibration bits are used to calibrate a main-DAC. The errors of the current sources in the main-DAC are estimated as a foreground calibration method does during booting and then are used to compute the calibrated outputs. The disadvantage of the prior art is requiring a sub-DAC and additional calibration bits, which increases the area overhead and the complexity of the circuit design.
T. Chen and G. Gielen published in IEEE J. Solid-State Circuit, vol. 42, No. 11, pp. 2386-2394, November 2007 a paper “A 14-bit 200-MHz Current-Steering DAC with Switching-Sequence Post-Adjustment Calibration,” wherein a current comparator is used to compare the current values of the MSB current sources, and digital control circuits sort the MSB current sources by their current values and rearrange the switching sequence of the MSB current sources. By pairing a small current source with a large one, the output current can approximate an average value to reduce the output error. However, the prior art requires a great amount of digital control circuits to sort the current sources and rearrange the switching sequence.
According to the discussion above, a great area overhead and high design complexity are the main issues for design high-resolution data converters.